To answer this question we need to understand some of the requirements and operational characteristics of Emergency Shutdown (ESD) systems and the criteria that determine the frequency that Safety Integrated Functions (SIF) must be proof tested.
Requirements and operational characteristics
A recurring problem associated with ESD systems is that in the normal course of events they are never exercised or called on to operate. For years at a time the ESD valve may remain open. It cannot be fully tested (full stroke closing time and ability to shut tight under design pressure differential) too regularly because that testing disrupts processes that may take days to shutdown and restart and cost millions of Rand of lost or off-specification production.
While the ESD valve remains open, valve components may be eroding, corroding or becoming fouled with scale or process line debris such as rust, scale, welding rod or other entrained foreign matter. At the same time the actuator mechanism may also be degrading. These conditions may negatively affect the ESD valve’s performance causing it to freeze, to take an extended time or to take a reduced time to achieve full stroke.
Plant owners need a way to increase their confidence in the ability of the ESD valve to perform as designed. The alternative is to resort to frequent and costly plant shutdowns required to perform a full test on the ESD valve in order to retain the designed SIL of the SIF.
SIL and full test frequency
The required SIL level for a SIF can be evaluated based on:
* The consequences of failure of a safety device.
* The frequency or exposure time to that risk.
* The possibility of avoiding that risk.
* The probability of occurrence of that risk.
The SIF is designed and components for the SIS loop selected based on:
* Redundancy design (Hardware Fault Tolerance).
* Manufacturer supplied information on failure modes and life spans (Total failure rate and Failure Rate (Dangerous)).
A suitable design will result in being able to calculate the target PFD (Probability of Failure on Demand) to meet the required SIL level.
At the point of successful commissioning of a SIS, the PFD of the testable components of the SIS is zero. This PFD increases as a function of elapsed time since last full test (commissioning) and Failure Rate (Dangerous). Once sufficient time has passed, the PFDavg will reach the target PFD. This determines the point at which full testing must be repeated to maintain the design SIL level (SIL2 for our hypothetical application).
Figure 1 illustrates how PFD for our hypothetical ESD valve increases over time. Each time the Proof Test Interval is reached (one year in this illustration) the owner must shut down the associated plant and execute a full test, returning the PFD to the residual risk line.
Extending the test interval
Key to understanding the value of Partial Stroke Testing of valves is the fact that the PFD is a result of the aggregation of the PFDs of the individual components of the SIF loop.
This is illustrated in Figure 2, where the overall PFD curve of Figure 1 is shown as the sum of:
a. PFD of non-testable components.
b. PFD of components whose failure modes are only testable through full testing.
c. PFD of components testable whose failure modes are testable through partial testing.
A second and equally important factor is an understanding of what is and what is not tested by PST – and this Proof Test Coverage (PTC) is dependent on the components that are exercised by the PST and those components that are not exercised by the PST. For instance a PST will not be able to test the leak-tightness of the ESD valve. Table 1¹ lists some examples but is not definitive.
If the area C of Figure 2 can be reduced then the period of time taken for PFDavg to rise to meet the target PSD of the SIF will be extended – i.e. the full proof test interval will be extended. This is exactly what partial stroke testing achieves.
Figure 3 illustrates the impact of partial stroke testing on full proof test interval.
By performing a PST on a regular basis (once a month in our hypothetical case) the residual risk (area A in Figure 2) and the risk associated with failures not tested by a partial stroke test (area B in Figure 2) remain unchanged, but it is clear that the contribution of area C to the PFDavg is now minimal. Each time a PST is performed the PFD is returned to the curve representing (the static residual risk) A + (the time dependent risk) B of risks not tested by the PST.
Depending on loop configuration and equipment selection a PST strategy can detect between 30% and 70% of ESD valve failures that would otherwise be classified as dangerous undetected failures² and according to Invensys the time between full proof tests may be increased by a factor of from 3 to 7 times that required without PST.
Microprocessors boost PTC
As the economic and safety benefits of PST have been recognised in SIS, there have been many advances in how PST is implemented. Modern systems use microprocessor controlled positioners for ESD actuation and partial stroke testing. These CPU-based units provide continuous closed loop position control, and can be configured to control percentage of test stroke movement (often between 10% and 20% of stroke for a short period) as well as rate of movement. Recording of test results, including aspects such as valve movement signatures, is fully automated. Consequently a far higher level of proof test coverage is achievable, lowering the residual risk and extending required full test intervals.
Depending on positioner design, PSTs can be initiated in many different ways:
* Automatically though scheduled actuation configured within the positioner itself.
* Manually through a local or remote head of the positioner.
* Manually or automatically through scheduled events in the SIS logic solver/ESD system or from other host systems via the supported protocols such as HART, Profibus PA, Foundation Fieldbus and FoxCom.
Cost justification
Since full proof testing is required less frequently it is clear that PST will result in:
* Lower costs (labour and materials) related to full proof testing.
* Lower impact on manufacturing (less lost production, shutdown/start-up off-specification product, flushing).
These two factors on their own can in many cases immediately support investment in PST technology.
There is also a third potential benefit that is less apparent:
* The potential for lower capital costs and associated lifecycle costs of components of the SIF loop.
This may be achievable where the reduced contribution of the risk testable through PST results in a SIF that will meet a higher SIL rating – for instance SIL3 instead of SIL2. Thus a PST strategy can, in some instances, avoid the need to install redundant equipment to achieve a required SIL rating.
For Ex and IS applications
The V&A Eckardt positioners SRD960 (EEx d) and SRD991 (for intrinsic safety zones) are certified for use in safety applications up to SIL3 and incorporate integral partial stoke testing to reduce PFD in any ESD valve loop. Using the extended diagnostics package, proof test coverage can be maximised allowing plant owners to extend full proof test intervals and simultaneously reduce risk.
These benefits translate to direct bottom line savings which can be of the order of millions of Rands per year in certain applications. This is why the V&A Eckardt positioners are the positioner of choice for major multinationals like BASF, Petronas and Saudi Aramco.
Fitting or retrofitting of suitable positioners is simplified where the positioner supplier has an extensive range of standard brackets for the fitting of their positioners to almost any known make and figure of positionable valve and where the configuration of the positioners is capable of being customised through multiple interface signal possibilities and communications protocols.
Sources:
1,2 ISA, adapted from ISA Expo 2005 Technical Conference: Partial Stroke Testing: Implementing for the right reasons; http://tinyurl.com/c5f2eb6
For more information contact Fred Venter, Valve & Automation, +27 (0)11 397 2833, [email protected], www.valve.co.za
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