An increasing number of products today include a combination of different signals such as analog, digital and timing. In order to ensure proper performance of a device under test, the measurement system used to validate these products needs to be able to both generate and acquire different types of signals.
The term mixed I/O refers to a product or system that has the capability to handle varying signal types. Designers and manufacturers need an effective means to test electrical components and products.
An example of a device that would require a mixed I/O test system would be an analog-to-digital converter (ADC). Since an ADC takes an analog signal and converts it to a digital signal, testing an ADC requires creating an analog signal and acquiring a digital signal. In addition, most ADCs need a clock or timing signal to tell it when to make these conversions; in turn, the ADC outputs a timing signal to indicate that the conversion is completed. Therefore, our test system now requires generating analog and timing signals and acquiring digital and timing signals.
Another requirement of our test system that may not be too apparent is the order in which these measurements occur. It would be ineffective if the digital measurement were made before the ADC actually converted the analog signal.
The most important aspect of a mixed I/O measurement system is the timing and synchronisation of the individual measurements. The main goal of synchronisation is to correlate measurements in time. How tightly a system needs to be correlated depends on the sample rate (or how fast) generated data needs to be acquired.
Single board
A myriad of vendors offer multifunction data acquisition boards to answer the need for mixed I/O testing. These boards include some combination of the analog, digital, and timing functionality. Since all of this capability is designed into one device, it is natural to assume that these different functions can all be synchronised. However, different functions of these boards have varying sample rates. In most cases, the digital I/O of these multifunction boards is static, which means that they cannot use a clock signal to dictate operation, but instead rely on software commands.
If the intention is to perform mixed I/O tests with a single multifunction board, there are a few things that should be verified with the vendor before creating the test. The first thing to understand is the basic specifications of the board and ensure that the number of channels and sampling rate are sufficient for the test. The next aspect to verify is if these functions can be used simultaneously and are correlated to the same internal clock. If the different functionalities of the board share the same internal clock, then the only delays experienced will be due to internal circuitry and are generally minimal. Finally, an often-overlooked feature critical for any measurement system, the software driver and the application programming interface (API) need to support and expose the ability to correlate the measurements together.
Multiple boards
Some applications require either higher channel count or different functionality than provided in a single board. This means sometimes it is necessary to develop measurement systems using multiple boards. In terms of mixed I/O tests, using multiple board systems is a very common approach because it allows the designer of the test system to build a custom system using individual measurement modules as the building block.
As opposed to a single device with a shared clock, multiple boards require implementing one of three different synchronisation schemes: trigger level, sample clock level, or reference clock level. To demonstrate these different schemes, let us use an example of test system which includes three different modules: one to handle analog output signals, one to handle analog input signals, and one to handle digital input and output signals.
Trigger level
This synchronisation scheme involves sharing a single trigger signal to all three devices. Once this trigger is received, each device will begin operating on its own internal sample clock. At relatively slow sample rates (<50 KS/s), this scheme is certainly adequate. However, at high speeds a few factors may come into play such as delay and drift.
Delay refers to the difference in time it takes for the trigger to be received at all the modules. Although, reducing the path length from the source of the trigger to the different modules can minimise this amount of time, an amount of delay will always be present.
Drift of clocks occurs when different clocks operate independently and small errors in these clocks accumulate over time. In the trigger level scheme, each of the three modules in our example uses its own clocks for operation so they are susceptible to drift. Drift can be minimised by either using modules with high-quality clocks or by using either the sample or reference clock level synchronisation schemes.
Sample clock level
Sample clock synchronisation is when the multiple modules share the same sample clock to know when to convert. So in our example, we would send the sample clock of one module to the other two modules and all three would share the same clock. This scheme greatly reduces effects of both delay and drift. However, another issue still affects the system: skew.
Skew is the amount of shift between the clock signals from one module to the next. External wiring or internal circuitry of each module causes this. Say it takes 5 ns for the sample clock from the source module to reach the second module and another 5 ns for it to reach the third module. Each time a conversion takes place, the first module will be 5 and 10 ns ahead of the second and third module respectively. However, skew is generally a few ns, so unless sampling is performed at high speeds (>1 MS/s) skew will have a minimal affect on the samples.
Reference clock level
This scheme is particularly valuable for high-speed measurements. Instead of using one clock and sending it to multiple modules, as in the sample clock scheme, now a high precision reference clock is used to adjust the sample clocks on each device. By using a reference clock, the affects of drift and skew are both alleviated. Certain measurement hardware has this level of synchronisation built in, such as PXI (PCI extensions for instrumentation). This synchronisation is achieved by a method called phase-lock looping (PLL).
A module with PLL circuitry monitors a reference clock and periodically compares the phase of the reference clock with its own sample clock. The actual sample clock of the module gives feedback into a comparator along with the reference clock. If there is any phase difference, the sample clock is then adjusted back in phase with the reference clock. Since this is done periodically and simultaneously on all modules, the individual sample clocks cannot stray too far from the reference frequency. This process mitigates the affects of drift and skew.
Putting it all together
Returning to the ADC example introduced at the beginning of the article, let us determine what synchronisation factors we are dealing with. Assume we want to run a test on ADCs coming from an assembly line. We know these are 5 MS/s ADCs. Therefore, we want a test system that can perform at the highest rate of our ADC so our test system needs to at least be able to sample at 5 MS/s.
Assuming this is a 12 bit ADC, it will be producing 12 digital signals (one for each bit) at a rate of 5 MS/s. Most likely this means we will need a dedicated digital board. We will also need a way to generate a clock and analog signal. This functionality can be found in a multifunction data acquisition board.
So we now know we need a multiple board system. This means that we need to choose the best synchronisation scheme for our test. Since it is imperative that the ADC finishes the conversion before we read the digital lines, we want to ensure that skew does not factor into our system (especially if this test is to run for a high number of samples ie 10 million samples or 20 seconds). This means that our best test system would include reference level synchronisation such as PLL.
When designing a mixed I/O system, first determine how fast the test system needs to be and how many channels of each signal type are required. If multiple board system approach is chosen, make sure that the timing scheme provides an acceptable level of synchronisation. This does not require being an expert on synchronisation and timing or measurement systems, but a basic understanding of the issues discussed will prove invaluable in ensuring an accurate test system.
National Instruments
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